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The packaging industry is adopting new technologies to deal with the problem of chip heat dissipation

In order to solve the problem of heat dissipation, packaging manufacturers are exploring various methods

Some overheated transistors may not have a great impact on reliability, but the heat generated by billions of transistors will affect reliability. This is especially true for ai/ml/dl designs. High utilization will increase heat dissipation, but heat density will affect every advanced node chip and package, which are used in smartphones, server chips, ar/vr and many other high-performance devices. For all of these, DRAM layout and performance are now the primary design considerations.

No matter how novel the architecture is, most DRAM based memories still face the risk of performance degradation due to overheating. Volatile memory refresh requirements (as a standard indicator, about every 64 milliseconds) exacerbate the risk.”When the temperature rises above 85 ° C, the charge on the capacitor needs to be refreshed more frequently, and the device will shift to a more frequent refresh cycle, which is why when the device becomes hotter, the charge leaks faster from these capacitors. Unfortunately, the operation of brushing the charge is also a current intensive operation, which will generate heat inside the DRAM. The hotter the weather, the more you need to update it, but you will continue Keep making it hotter and the whole thing will fall apart.”

In addition to DRAM, heat management has become crucial for more and more chips. It is one of more and more interrelated factors, which must be considered in the whole development process. The packaging industry is also looking for ways to solve the heat dissipation problem. Choosing the best package and integrating chips in it is very important for performance. Components, silicon, TSV, copper pillars, etc. all have different coefficient of thermal expansion (TCE), which will affect the assembly yield and long-term reliability.

The BGA package of popular flip chip with CPU and HBM is about two500 at presentmmtwo。 A large chip may become four or five small chips. In general, this trend will continue, because all i/o must be owned so that these chips can communicate with each other. So it can disperse heat. For applications, this may help you. But some of the compensation is because you now have i/o driving between chips, and in the past you needed an internal bus in silicon chip to communicate.

In the end, this becomes a system challenge, and a series of complex trade-offs can only be handled at the system level. Many new things can be achieved through advanced packaging, but now the design is much more complex. When everything is so closely combined, there will be more interactions. The flow must be checked. The power distribution must be checked. This makes it very difficult to design such a system.

In fact, some devices are very complex, and it is difficult to easily replace components in order to customize these devices for applications in specific fields. This is why many advanced packaging products are suitable for high-volume or price flexible components, such as server chips. The demand for materials for manufacturing processes with enhanced heat dissipation has been growing strongly.

Advances in simulation and testing of chipet modules

Engineers are looking for new ways to analyze the package reliability before the package module is built. For example, Siemens provided an example of a module based on a dual ASIC, which contains a fan out redistribution layer (RDL), which is installed on top of a multilayer organic substrate in a BGA package. It uses two models, one for RDL based WLP and the other for multilayer organic substrate BGA. These packaging models are parametric, including substrate layer stacking and BGA before EDA information is introduced, and support early material evaluation and chip placement selection. Next, EDA data is imported. For each model, the material diagram can give a detailed thermal description of the copper distribution in all layers.

Quantitative thermal resistance

It is well known how to transfer through silicon chip, circuit board, glue, Tim or package cover. There are standard methods to track the temperature and resistance values at each interface, which are functions of temperature difference and power.

“The thermal path is quantified by three key values – the thermal resistance from the device junction to the environment, the thermal resistance from the junction to the housing (top of the package), and the thermal resistance from the junction to the circuit board.”

Detailed thermal simulation is the cheapest way to explore material and configuration options.”Running the simulation of a chip usually identifies one or more hot spots, so we can add copper to the substrate below the hot spots to help heat dissipation or replace the cover material and add radiators, etc. for multiple chip packages, we can change the configuration or consider adopting new methods to prevent thermal crosstalk. There are several ways to optimize high reliability and thermal performance,”

After the simulation, the packaging company performs experimental design (DOE) to achieve the final packaging configuration. However, due to the time-consuming and higher cost of using specially designed test vehicles, simulation is used first.

Select Tim

In the package, more than 90%of the heat is emitted from the top of the chip to the radiator through the package, which is usually an anodized aluminum substrate with vertical fins. A thermal interface material (TIM) with high thermal conductivity is placed between the chip and the package to help transfer heat. The next generation Tim for CPU includes sheet metal alloys (such as indium and tin) and silver sintered tin, with conduction power of 60 w/mk and 50 w/mk respectively.

As the company transitions from large SOC to small chip module, more kinds of Tim with different characteristics and thickness are needed.

YoungDo kweon, senior director of Amkor R & D, said in a recent speech that for high-density systems, the thermal resistance of Tim between chip and package has a greater impact on the overall thermal resistance of package modules.”The power trend is increasing sharply, especially in logic, so we are concerned to keep the junction temperature low to ensure reliable semiconductor operation,” kweon said. He added that although Tim suppliers provide thermal resistance values for their materials, in practice, the thermal resistance from chip to package is affected by the assembly process itself, including the bonding quality and contact area between chip and Tim. He pointed out that testing with actual assembly tools and bonding materials in a controlled environment is essential to understand the actual thermal performance and select the best Tim for customer qualification.

Holes are a special problem.”The way materials behave in packaging is a considerable challenge. You have mastered the material properties of adhesives or glues, and the way materials actually wet the surface will affect the overall thermal resistance of the material, that is, the contact resistance,” said parry of Siemens.”And it largely depends on how the material flows into very small defects on the surface. If the defect is not filled with glue, it represents additional resistance to heat flow.”

Treat heat in different ways

Chip makers are expanding the range of solutions to heat restrictions.”If you reduce the size of the chip, it may be a quarter of the area, but the package may be the same. Randy white, the project manager of memory solutions of Shide technology, said that there may be some signal integrity differences because the bonding wire of the external package enters the chip.”The wire is longer and the inductance is larger, so there is an electrical part. If the area of the chip is halved, it will be faster. How to dissipate so much energy in a small enough space? This is another key parameter that must be studied.”

This has led to a lot of investment in cutting-edge bonding research, at least for now, the focus seems to be hybrid bonding.”If I have these two chips and there is almost no bulge between them, there will be an air gap between these chips,” said woo of Rambus.”This is not the best way to conduct heat up and down. Some things may be used to fill the air gap, but even so, it is not as good as direct silicon contact. Therefore, hybrid direct bonding is something people are doing.”

However, hybrid bond synthesis is expensive and may still be limited to high-performance processor applications. TSMC is one of the only companies to provide this technology at present. Nevertheless, the prospect of integrating photonics into CMOS chips or Gan on silicon is still huge.


The original idea behind advanced packaging is that it can work like Lego bricks – small chips developed at different process nodes can be assembled together and can reduce thermal problems. But there are also trade-offs. From the perspective of performance and power, the distance of signal transmission is very important, and the circuit that is always on or needs to be kept partially off will affect the thermal performance. It’s not as simple as it seems to be to divide the mold into multiple parts just to improve production and flexibility. Every interconnection in the package must be optimized, and the hotspot is no longer limited to a single chip.

Early modeling tools that can be used to exclude or exclude different combinations of small chips provide a great impetus for designers of complex modules. In this era of increasing power density, thermal simulation and the introduction of new Tim are still essential.