At TSMC’s 2022 Technology Forum, TSMC announced the status and planning of 7Nm to 2nm advanced processes, as well as characteristic processes including RF/networking, CMOS image sensing, MEMS and power management. Among them, 2nm process will be mass produced in 2025.
TSMC said that covid-19 has accelerated the digital transformation in the past two years, and as electronic devices have become more intelligent and highly connected, in the face of the demand for more intelligent edge devices and large-scale computing capabilities, high energy efficiency and low energy consumption have become particularly important for edge devices, while structural growth has led to a shortage of advanced and mature processes. Therefore, TSMC continues to increase its R & D investment to provide the best technology, and continues to expand its investment in advanced process and mature process capacity.
2nm process will be mass produced in 2025
TSMC’s goal in advanced technology is to provide industry-leading technology development at a stable and predictable speed, strengthen the performance, power consumption and density (PPA) of each process technology, and maintain the compatibility of design rules to realize the reuse of silicon smart wealth.
Specifically, TSMC’s process promotion plan:
7 nm family:
TSMC’s customer product portfolio using N7 and N6 technologies continues to expand, from smartphones, CPUs, GPUs and xpus to RF and consumer electronics applications. By the end of 2022, the cumulative number of finalized product designs will exceed 400.
5 nm family:
TSMC’s 5-nanometer technology has entered its third year of mass production, supporting product applications in smart phones, 5g, AI, networks and high-performance computing industries. TSMC applies its mass production experience not only to the improvement of yield, but also to the improvement of performance, design rules and chip density. Through continuous improvement of N5 and N4 technologies, it is expected that more than 150 product designs will be finalized by the end of this year.
At present, TSMC has added N4, n4p and n4x technologies to its 5nm family to provide continuous PPA upgrades for upcoming 5nm products. It is reported that from N5 to n4x, the performance has been improved by 15%and the chip density has been increased by 6%, while maintaining the compatibility of design rules to achieve design reuse, more functions and better specification improvement.
In 2021, TSMC launched the upgraded N5A of semiconductor technology for automotive industry applications, and plans to pass the aec-q100 grade-2 certification in the third quarter of this year.
3 Nanometer family:
TSMC 3 nano process technology continues to adopt FinFET semiconductor structure, and believes that the performance and technical maturity of this process will best meet the needs of the industry. The N3 process is progressing smoothly as planned and will be mass produced in the second half of 2022, followed by n3e in the second half of 2023.
This year, TSMC introduced the innovation of TSMC finflextm architecture on 3-nanometer technology. It combines the innovation of process and design, and provides the ultimate design flexibility, so as to optimize high performance, low power consumption or achieve the balance between the two. It provides significant chip design advantages and flexibility, and provides a powerful platform for product innovation. We know that reducing the number of fins is very important to improve PPA. The finflex innovation of TSMC is a key breakthrough. By mixing different component heights, different component heights can be achieved in a design block.
TSMC finflex architecture further improves the product performance, power efficiency and density of 3-nanometer family technology, so that chip designers can use the same design tools on the same chip to select the best fin structure to support each key functional block. There are 3-2 fin, 2-2 fin, and 2-1 fin structures to choose from, and their characteristics are as follows:
• 3-2 fins – the fastest frequency and highest efficiency to meet the highest computing requirements
• 2-2 fins – efficient performance, achieving a good balance between performance, power efficiency and density
• 2-1 fins – ultra high efficiency, lowest power consumption, lowest leakage and highest density
Finflex innovation enables n3e to realize the full generation miniaturization from N5, providing complete platform support for mobile and HPC applications, and will have stronger performance, power and lower process complexity.
2 nanometer family:
In the past 15 years, TSMC has been studying nanosheet transistors and believes that N2 is a suitable process for introducing nanosheet transistors, which will improve the speed and power of the whole generation and help customers maintain competitiveness. At present, the development of N2 is progressing smoothly as planned and is expected to be mass produced in 2025.
With the help of nano chip transistor and Design Technology Collaborative Optimization (DTCO), the performance and power advantages of TSMC N2 have been improved by a generation. Compared with n3e, the speed is increased by 10-15%at the same power consumption, or the power consumption is reduced by 25-30%at the same speed. Due to the excellent low VDD performance of nano chip transistor, the performance of N2 is improved by 15%at normal Vdd and the same power consumption, and the advantage is expanded to 26%at low VDD (0.55v).
In the future, TSMC is optimistic about the development after N2, especially the innovation in new transistor structures, new materials, continuous miniaturization and new conductor materials.
Over the years, the evolution of standard semiconductor architecture has shifted from planar transistors to fin field effect transistors (FinFETs), and will once again develop to nano chip transistors. Even outside the nanosheets, TSMC sees many possible directions, including CFET (nFET and pFET of vertical stack).
In addition, TSMC is also looking forward to breakthroughs in 2D materials, 1D carbon nanotubes and other aspects to overcome the challenges of chip mobility while constantly miniaturizing. In the future, TSMC will continue to explore the transistor architecture and use new materials such as 2D materials and carbon nanotubes.
In order to solve the problem of reducing the spacing of key processes, TSMC began to use EUV exposure equipment and multiple exposure technology on n7+. In the future, TSMC will introduce high NA EUV exposure equipment in 2024 to develop the relevant infrastructure and exposure solutions required by customers to support innovation.
Write at the end
In addition to the promotion and development of TSMC in advanced technology, TSMC also invested a lot in special technology. It is understood that in recent years, the compound annual growth rate of TSMC’s investment in special technologies has exceeded 64%, almost three times the past investment rate. In the next few years, it is expected to further expand its special process capacity. TSMC predicts that by 2025, the capacity of special processes will increase by nearly 50%.
TSMC continues to improve productivity and maximize output through intelligent manufacturing innovation. Over the past three years, TSMC’s capital expenditure has more than doubled, from less than $15billion in 2019 to $30billion in 2021 and $40 to $44billion in 2022, building capacity for advanced process, mature process and 3dfabric.
TSMC’s new 28 nanometer wafer plant in Nanjing is expected to start mass production in the fourth quarter of this year. At the same time, its wafer plant in Arizona is under construction, and it is expected to mass produce 5-nanometer process in 2024. TSMC is also building a new plant line in Kumamoto, Japan, and expanding its planned capacity to provide wafer manufacturing services with 12/16 nm and 28 nm family technologies. It is expected to start mass production in 2024.